Design and Layout Techniques for the Optimization of nMOS SPDT Series-Shunt Switches in a 130nm SiGe BiCMOS Technology

Abstract

This work investigates various design and layout optimization approaches for MOSFET-based series-shunt, single-pole double-throw (SPDT) switches in a commercially-available 130 nm silicon-germanium (SiGe) BiCMOS technology. The incorporation of deep-trench isolation, additional substrate contacts, and additional gate resistance for the series nMOS device are examined, and the impact of these design and layout optimizations on the switches insertion loss, bandwidth, isolation and linearity performance have been quantified across frequency. This experiment has yielded a SPDT switch with an insertion loss of - 1.4 dB, -1.5 dB, and -2.0 dB, at 5.8 GHz, 10 GHz, and 20 GHz, respectively, and an input-referred third-order intercept point (II P3) of 21 dBiu at 9.5 GHz, without the use of any process adders or additional supply voltages.