Line Replacement Algorithm for L1-scale Packet Processing Cache

Abstract

It will become a serious problem to increase power consumption of routers resulting from explosive increase of network traffics caused by IoT data, big data, and so on. Table lookups in packet processing are known as a bottleneck of the router from the points of both processing performance and power consumption. Packet Processing Cache (PPC), which accelerates the table lookups and reduces the power consumption of them by using cache mechanism, was proposed. However, it is difficult for PPC to obtain high cache hit rate because the size of PPC should be small, such as a L1 cache of processors, to get higher access speed. For this reason, an effective line replacement algorithm was considered in this study for reducing a cache miss without increasing the cache size. First, defects of applying typical line replacement algorithms to PPC were examined. Secondly, two algorithms, LRU Insertion Policy (LIP) and Elevator Cache (ELC), and improved algorithms of LIP and ELC called LIP1, LIP2, ELC1, and ELC2 were considered for improving the above defects. In simulation, it was shown Elevator Cache could reduce the cache miss by at most 17.4% compared with Least Recently Used, which applied to many cache systems.