{"title":"A power-aware quad-voltage H.264 encoder chip for wireless panoramic endoscope applications","authors":"An-Tia Xiao, Shiang-Ren Yang, Yuan-Hsiang Miao, Ching-Hwa Cheng, Jiun-In Guo","doi":"10.1109/VLSI-DAT.2015.7114537","DOIUrl":null,"url":null,"abstract":"Voltage scaling is an efficient way to reduce dynamic power consumption for digital circuits. In this paper, a hierarchical multiple voltage (HMulti-Vdd) technology is proposed to design a power-aware H.264 intra-frame encoder for wireless panoramic endoscope applications. The proposed design adopts quad supply voltages to reduce power consumption without performance degradation. A progressive voltage difference technique is adopted in the proposed design for preventing from the penalty from using level shifters on performance and power consumption. The quad-voltage test chip has been successfully validated and has shown a 40% average reduction of power consumption, as compared to the same design using a single supply voltage.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI Design, Automation and Test(VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT.2015.7114537","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Voltage scaling is an efficient way to reduce dynamic power consumption for digital circuits. In this paper, a hierarchical multiple voltage (HMulti-Vdd) technology is proposed to design a power-aware H.264 intra-frame encoder for wireless panoramic endoscope applications. The proposed design adopts quad supply voltages to reduce power consumption without performance degradation. A progressive voltage difference technique is adopted in the proposed design for preventing from the penalty from using level shifters on performance and power consumption. The quad-voltage test chip has been successfully validated and has shown a 40% average reduction of power consumption, as compared to the same design using a single supply voltage.