ESD protection of the high voltage tolerant pins in low-voltage BiCMOS processes

Abstract

A methodology. for achieving ESD devices by increasing the breakdown voltage of the protection of high voltage pins in a low voltage blocking junctions for ESD devices in 0.5pm technology is presented. The methodology utilizes eilicient mask level control of both the blocking BiCMOS and CMOS processes. lr Hlgh Voltage junction and the triggering characteristics of the *5v . .. . . . t.. . .. . , ESD devices without the addition or chance in anv -. process steps. The methodology was validated by numerical simulation and experimental measurements for the case of dualdirection SOV tolerant onship ESD protection of thin fh resistors in a N BiCMOS process. The methodology was also applied to the case of tnrnon voltage increase of an extended drain SCR ESD protection device in a 5V CMOS process.