Qin Ke, Hang Yu, Yan Li, Siguang Ma, D. Xi, Rui Chen
{"title":"A 32-Channel Time-to-Digital Converter with 20-ps Resolution for ToF Applications","authors":"Qin Ke, Hang Yu, Yan Li, Siguang Ma, D. Xi, Rui Chen","doi":"10.1109/ICCS56666.2022.9936246","DOIUrl":null,"url":null,"abstract":"Single-photon avalanche diodes (SPAD) enable sensitive detection of single photons under ultra-weak light conditions. Combined with direct time-of-flight (ToF) measurements, SPAD sensors are widely used in 3D imaging systems. Time-to-Digital Converter (TDC) can accurately measure time intervals in picoseconds, which is widely used for direct TOF measurements. This paper proposes a 32-channel TDC of two-level architecture containing a delay locked loop (DLL) and a vernier delay line (VDL) loop to increase timing accuracy. Designed in a 180 nm CMOS process, the TDC occupies an area of 4.1 mm $\\times$ 3.6 mm and achieves 20 ps resolution at 2 Msps measurement rate.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"188 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCS56666.2022.9936246","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Single-photon avalanche diodes (SPAD) enable sensitive detection of single photons under ultra-weak light conditions. Combined with direct time-of-flight (ToF) measurements, SPAD sensors are widely used in 3D imaging systems. Time-to-Digital Converter (TDC) can accurately measure time intervals in picoseconds, which is widely used for direct TOF measurements. This paper proposes a 32-channel TDC of two-level architecture containing a delay locked loop (DLL) and a vernier delay line (VDL) loop to increase timing accuracy. Designed in a 180 nm CMOS process, the TDC occupies an area of 4.1 mm $\times$ 3.6 mm and achieves 20 ps resolution at 2 Msps measurement rate.