Design Optimization and Surge Current Capability of 4H-SiC Lateral Deep P+ JBS Diode on Thin RESURF Layer

Abstract

In this paper, we explore the optimization of "saddle" type finger layout for lateral SiC RESURF (Reduced Surface Electric Field) diodes where concave/convex finger ends combined with mesa etch isolation achieve over 82% of the inner cell breakdown voltage. Furthermore, added deep P+ JBS pattern near the anode Schottky contact significantly improves robustness against field crowding when cell pitch/finger width is reduced to densify the chip. Improved surge current capability compared with pure Schottky structure is investigated through mix-mode TCAD simulation. The proposed design methodologies offer guidance for future efforts toward realizing a monolithic SiC high voltage integrated circuit.