Frequency Stabilization of a VCDRO by Microcontroller Supported Frequency Lock Loop

P. Manojlovic, V. Smiljakovic, S. Jovanovic
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引用次数: 0

Abstract

The paper presents frequency stabilization of a VCDRO operating at 11 GHz by using a frequency lock loop supported by microcontroller. The signal from a PLL synthesizer is used as a reference signal in the FLL in order to obtain a signal with characteristics like one originating from a free- running VCDRO having, in the same time, stability close to a signal from PLL. The two signals are compared at 40 MHz band where a IF filter is designed in order to limit a stability difference between a VCDRO and PLL. A control signal within the FLL loop is realized with microcontroller that ensures a very stable operation over a wide temperature range. The signal obtained in the presented way meets the desired stability with very low level of spurious signals and meets all requirements for LO signals in modern microwave systems.
单片机支持锁频环的VCDRO稳频
本文介绍了利用单片机支持的锁频环实现工作在11ghz频率下的VCDRO稳频。来自锁相环合成器的信号被用作FLL中的参考信号,以便获得与来自自由运行的VCDRO具有类似特征的信号,同时具有接近锁相环信号的稳定性。在40 MHz频段比较两个信号,其中设计了中频滤波器,以限制VCDRO和锁相环之间的稳定性差异。FLL环路内的控制信号由微控制器实现,确保在很宽的温度范围内稳定运行。该方法所获得的信号在具有极低杂散信号水平的情况下满足了期望的稳定性,满足了现代微波系统对本LO信号的所有要求。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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