Single-poly bipolar transistor with selective epitaxial silicon and chemo-mechanical polishing

Abstract

Fabrication of bipolar transistors employing selective epitaxial growth (SEG) and chemo-mechanical polishing (CMP) is demonstrated. The SEG/CMP combination allows for lithography-limited isolation and results in inherently planar surfaces. The pedestal structure made possible by these technologies facilitates reduction of extrinsic base-collector capacitance and reduces the edge leakage common in SEG structures. The pedestals protect the SEG sidewalls from any potential contaminants or oxidation-induced stress during subsequent processing, and hence help eliminate any induced leakage.<>