{"title":"FPGA Implementation of Multi-carriers PWM Technique for Modular Multi-level Inverter","authors":"Elmoatez Billah Atoui, T. Mesbah, Hamza Atoui","doi":"10.1109/ICASS.2018.8651974","DOIUrl":null,"url":null,"abstract":"The present paper proposes the implementation of multi-carriers PWM technique based-on Field Programmable Gate Array (FPGA) for Modular Multilevel Converter (MMC). Focus-on level shifted PWM, the Phase Disposition PWM (PD-PWM) has been analyzed for 3-phase 5-level Modular Multilevel Inverter (MMI). A complete digital controller of PD-PWM technique was designed using the Hardware Description Language (VHDL). The developed controller contains four principal blocks; programmable clock divider block, ROM phases generator block, up/down counter block for carriers generator and combinatorial block based-on comparators in order to generate the gate signals of each phase with dead time. Xilinx ISE and Modelsim are used as simulation software in order to verify and synthesize the behavioral and correctness of developed controller which are achieved. After implementation on Digilent Atlys FPGA board, the experimental gate signals waveforms are obtained via a digital oscilloscope.","PeriodicalId":358814,"journal":{"name":"2018 International Conference on Applied Smart Systems (ICASS)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International Conference on Applied Smart Systems (ICASS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASS.2018.8651974","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
The present paper proposes the implementation of multi-carriers PWM technique based-on Field Programmable Gate Array (FPGA) for Modular Multilevel Converter (MMC). Focus-on level shifted PWM, the Phase Disposition PWM (PD-PWM) has been analyzed for 3-phase 5-level Modular Multilevel Inverter (MMI). A complete digital controller of PD-PWM technique was designed using the Hardware Description Language (VHDL). The developed controller contains four principal blocks; programmable clock divider block, ROM phases generator block, up/down counter block for carriers generator and combinatorial block based-on comparators in order to generate the gate signals of each phase with dead time. Xilinx ISE and Modelsim are used as simulation software in order to verify and synthesize the behavioral and correctness of developed controller which are achieved. After implementation on Digilent Atlys FPGA board, the experimental gate signals waveforms are obtained via a digital oscilloscope.