High-power, high-efficiency digital polar doherty power amplifier for cellular applications in SOI CMOS

2016 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications (PAWR) Pub Date : 1900-01-01 DOI:10.1109/PAWR.2016.7440131

Varish Diddi, H. Gheidi, J. Buckwalter, P. Asbeck

引用次数: 6

Abstract

This paper presents a Digital Doherty Power Amplifier (DDPA) with high back-off efficiency. The main and peaking amplifiers are implemented in 180 nm CMOS SOI as Digital Power Amplifiers (DPAs) with 10 bit amplitude control. The Doherty combiner is implemented using external matching components on a PCB, with lumped elements synthesized to provide equivalent characteristics of impedance inverter and offset-line. Phase adjustment between main and peaking DDPAs allows optimization of efficiency. CW measurements for the DDPA at 900 MHz correspond to 33.1 dBm peak power with 55.5% efficiency. This is highest reported output power for CMOS Doherty amplifiers. The efficiency at 6 dB back-off reaches 52.5%.

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高功率，高效率的数字极性多赫蒂功率放大器，用于蜂窝应用的SOI CMOS

提出了一种具有高回退效率的数字多尔蒂功率放大器(DDPA)。主放大器和峰值放大器在180 nm CMOS SOI中实现，作为10位幅度控制的数字功率放大器(dpa)。Doherty组合器使用PCB上的外部匹配组件实现，集成了集总元件，以提供阻抗逆变器和偏置线的等效特性。主和峰值ddpa之间的相位调整允许优化效率。DDPA在900 MHz的连续波测量值对应于33.1 dBm峰值功率，效率为55.5%。这是CMOS多尔蒂放大器报道的最高输出功率。6db回退时的效率达到52.5%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2016 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications (PAWR)

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