Monte Carlo simulations of inverse channel versus implant free In0.3Ga0.7As MOSFETs

Abstract

A performance of two n-type III-V MOSFET based on an In0.3Ga0.7As channel architecture: a surface channel design with implanted source/drain contacts and a δ-doped, implant-free design, is compared when scaled to gate lengths of 35 nm, 25 nm and 18 nm. The transistor characteristics are simulated using ensemble heterostructure finite element Monte Carlo device simulations assisted by drift-diffusion simulations in a sub-threshold region. The Monte Carlo simulations include a calibrated quantum corrections for each of the scaled transistor and two interface related scattering mechanisms: interface roughness and interface phonons at the interface of polar-polar materials. The scaling of surface channel MOSFETs delivers an increase in the device on-current despite the negative impact of interface phonons, while the implant free MOSFETs scaled to 18 nm gate length suffer substantially from a largely enhanced scattering due to interface roughness and phonons.