A VLSI implementation of pipelined JPEG encoder for grayscale images

Abstract

A VLSI implementation of the DCT-based JPEG encoder customized for grayscale images is presented. The JPEG encoder mainly includes FDCT, quantization, run-length encoder and entropy encoding. The two-dimensional DCT is divided into two one-dimensional DCTs because of its separability property and a pipeline technique is adopted to achieve an efficient and optimized FDCT architecture. And then an eight-stage pipelined nonrestoring divider of quantization algorithm is put forward to reach a high operating frequency, and a complete divider is processed at each 8 clock cycles when the pipeline is full. Finally, the chip layout is carried out in a 0.13 µm CMOS technology. The estimated area and power consumption of the designed encoder are 0.283 mm2 and 260 mW, respectively. The proposed encoder is 100% compatibility with the JPEG standard and can be extended to a color application.