Implementation of large size multipliers using ternary adders and higher order compressors

Abstract

Recent FPGA architectures facilitate the efficient mapping of high order compressors to implement multi-operand additions. This feature can be used to improve the performance and area utilization of large size multipliers. In this paper we present an improved design approach utilizing ternary adders and Generalized Parallel Compressors, GPCs, for the addition of the partial products. Multipliers of different sizes ranging from 80 bits to 170 bits were implemented on Altera's Stratix III devices. The results of our proposed scheme are compared to the standard ripple-adder-based multipliers. On average, a delay reduction of 17.7% and area saving of 56.53% were achieved when using ternary adders. Using the GPCs with one level ternary adder, the average delay reduction is 18.7% and the average area saving is 24.1%.