A new SSS-OSELO technology for 0.15-/spl mu/m low-defect isolation

Abstract

A new isolation with single-Si/sub 3/N/sub 4/-spacer (SSS) OSELO technology is proposed. The features of the SSS OSELO process are low bird's beak penetration and low defect isolation, which are achieved by using low defect-density etching for the Si/sub 3/N/sub 4/ spacer formation, and lower growth-rate and/or a high-temperature oxidation ambient. The SSS OSELO technology allows the 0.15-/spl mu/m low-defect isolation and the fabrication of 1-gigabit DRAM cells.