{"title":"Design of a multifunctional small digital integrated circuit (IC) using 180nm CMOS Technology","authors":"Raviraj Singh, R. Khatri, R. Gurjar","doi":"10.1109/ICECA49313.2020.9297638","DOIUrl":null,"url":null,"abstract":"This article presents a multifunctional digital integrated circuit(IC)and the integrated circuit performs four tasks separately namely, 555 Timer, Multiplexer, Counter, and Flip-Flop. The certain task is chosen by selecting two-line input four output demultiplexers. The 555 timer IC performs three different modes such as monostable, astable, and bistable mode. These modes are chosen by a given input pattern. The design is delivered by a 1. 8V direct current supply with a difference ofO.lv. The proposed design consumes 11.41mW power which is reliable. These circuits are depicted by Semi-conductor Laboratory (SCL) 180nm Technology in Cadence Virtuoso Analog Design Environment.","PeriodicalId":297285,"journal":{"name":"2020 4th International Conference on Electronics, Communication and Aerospace Technology (ICECA)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 4th International Conference on Electronics, Communication and Aerospace Technology (ICECA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECA49313.2020.9297638","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This article presents a multifunctional digital integrated circuit(IC)and the integrated circuit performs four tasks separately namely, 555 Timer, Multiplexer, Counter, and Flip-Flop. The certain task is chosen by selecting two-line input four output demultiplexers. The 555 timer IC performs three different modes such as monostable, astable, and bistable mode. These modes are chosen by a given input pattern. The design is delivered by a 1. 8V direct current supply with a difference ofO.lv. The proposed design consumes 11.41mW power which is reliable. These circuits are depicted by Semi-conductor Laboratory (SCL) 180nm Technology in Cadence Virtuoso Analog Design Environment.