{"title":"Fault Localization and Full Error Correction in Radix2 Signed Digit-Based Adders","authors":"S. R. Alavi, K. Faez","doi":"10.1109/PACRIM.2007.4313214","DOIUrl":null,"url":null,"abstract":"In this paper, a new methodology to increase fault-tolerant and full error correction capabilities in self-checking adders based on the radix 2 signed digit (SD) representation is presented. The full error correction ability is indebted to \"locality\" property of carry propagation in this type of adder, in which the carry propagation is confined to neighbor digits. The second motive of using these adders is their computational speed. In fact, because the parity of the augends is preserved, the error produced by a single stuck-at fault can be detected by parity checker. As \"locality\" property of carry propagation prevents dissemination of error yielded by permanent faults, therefore, the location of faulty digit is found by using a recomputation with shifted operands method. Finally, after fault localization, the full error correction is performed by using a recomputation with triple shifted operands method.","PeriodicalId":395921,"journal":{"name":"2007 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PACRIM.2007.4313214","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
In this paper, a new methodology to increase fault-tolerant and full error correction capabilities in self-checking adders based on the radix 2 signed digit (SD) representation is presented. The full error correction ability is indebted to "locality" property of carry propagation in this type of adder, in which the carry propagation is confined to neighbor digits. The second motive of using these adders is their computational speed. In fact, because the parity of the augends is preserved, the error produced by a single stuck-at fault can be detected by parity checker. As "locality" property of carry propagation prevents dissemination of error yielded by permanent faults, therefore, the location of faulty digit is found by using a recomputation with shifted operands method. Finally, after fault localization, the full error correction is performed by using a recomputation with triple shifted operands method.