{"title":"VVC intra prediction decoder: Feature improvement and performance analysis","authors":"Aymen Zayed, N. Belhadj, K. Khalifa, M. H. Bedoui","doi":"10.1109/DTS55284.2022.9809895","DOIUrl":null,"url":null,"abstract":"Nowadays, streaming applications have been in great demand, especially due to covid-19 (teleworking, online teaching, virtual reality, etc.). In addition, artificial intelligence has become widely used especially in video processing domains, so a video with high quality improves the accuracy rate of this application. To meet these needs, the Versatile Video Coding standard (VVC) has appeared to give a high compression efficiency compared to high-efficiency video coding. This norm consists of a high complexity algorithm that offers an improvement in processing time and decreases the bit rate by 50 % thanks to several new compression techniques. In this context, we propose the implementation of an intra prediction decoding chain of this standard on a system on chip. In this work, we highlight the VVC feature enhancements, we present the suitable method for VVC intra-prediction decoder implementation on the PYNQ-Z2, and we provide profiling in terms of decoding time and power consumption. As a future work, this study is helpful to distinguish the block that will be a candidate for a Hardware acceleration.","PeriodicalId":290904,"journal":{"name":"2022 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DTS55284.2022.9809895","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Nowadays, streaming applications have been in great demand, especially due to covid-19 (teleworking, online teaching, virtual reality, etc.). In addition, artificial intelligence has become widely used especially in video processing domains, so a video with high quality improves the accuracy rate of this application. To meet these needs, the Versatile Video Coding standard (VVC) has appeared to give a high compression efficiency compared to high-efficiency video coding. This norm consists of a high complexity algorithm that offers an improvement in processing time and decreases the bit rate by 50 % thanks to several new compression techniques. In this context, we propose the implementation of an intra prediction decoding chain of this standard on a system on chip. In this work, we highlight the VVC feature enhancements, we present the suitable method for VVC intra-prediction decoder implementation on the PYNQ-Z2, and we provide profiling in terms of decoding time and power consumption. As a future work, this study is helpful to distinguish the block that will be a candidate for a Hardware acceleration.