{"title":"A 35ns 16K PROM","authors":"R. Wallace, A. Learn, K. Schuette","doi":"10.1109/ISSCC.1980.1156026","DOIUrl":null,"url":null,"abstract":"This paper will cover a 16,384b PROM organized 2K × 8, fabricated on a 140mil square chip, with a typical 25ns access time and 600mW power dissipation.","PeriodicalId":229101,"journal":{"name":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1980.1156026","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
This paper will cover a 16,384b PROM organized 2K × 8, fabricated on a 140mil square chip, with a typical 25ns access time and 600mW power dissipation.