{"title":"A monolithic InSb charge-coupled infrared imaging device","authors":"R. Thom, F. Renda, W. Parrish, T. Koch","doi":"10.1109/IEDM.1978.189464","DOIUrl":null,"url":null,"abstract":"Monolithic charge-coupled infrared imaging devices (CCIRIDs) have been fabricated in InSb and infrared detection and readout with the arrays demonstrated. The CCIRIDs which have been operated are 20-element linear arrays incorporating lateral transfer from MOS detectors into an InSb CCD shift register. The 20-bit register is a four-phase, surface channel, overlapping gate CCD. The charge transfer efficiency (CTE) has been measured by electrical injection of signal using the fat zero (FZ) inputs. At fc= 100 kHz and 77°K, CTE is ≥0.995 operating with a FZ. The CTE is limited by parallel-edge surface state loss and correlates with the surface state density which is in the 5×1011- to 1012-cm-2-eV-1range for the devices tested. Charge integration in the photo-gates, transfer into the register, and serial read-out of the 20 detector signals have been demonstrated for the InSb CCIRIDs.","PeriodicalId":164556,"journal":{"name":"1978 International Electron Devices Meeting","volume":"93 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1978 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1978.189464","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
Monolithic charge-coupled infrared imaging devices (CCIRIDs) have been fabricated in InSb and infrared detection and readout with the arrays demonstrated. The CCIRIDs which have been operated are 20-element linear arrays incorporating lateral transfer from MOS detectors into an InSb CCD shift register. The 20-bit register is a four-phase, surface channel, overlapping gate CCD. The charge transfer efficiency (CTE) has been measured by electrical injection of signal using the fat zero (FZ) inputs. At fc= 100 kHz and 77°K, CTE is ≥0.995 operating with a FZ. The CTE is limited by parallel-edge surface state loss and correlates with the surface state density which is in the 5×1011- to 1012-cm-2-eV-1range for the devices tested. Charge integration in the photo-gates, transfer into the register, and serial read-out of the 20 detector signals have been demonstrated for the InSb CCIRIDs.