Low-power sequential access memory design

Abstract

This paper presents the design and evaluation of a sequential access memory (SAM) that provides low power and high performance by replacing address decoders with special locally-communicating sequencers. A test chip containing one 16/spl times/16-b SAM and one 64/spl times/16-b SAM (consisting of four 16/spl times/16-b banks) has been designed, fabricated, and evaluated using a 0.25-/spl mu/m CMOS process. With a clock frequency of 40 MHz at 1.2 V, the measured worst-case read power dissipations for the 16/spl times/16-b SAM and the 64/spl times/16-b SAM are 344 /spl mu/W and 358 /spl mu/W respectively, demonstrating power dissipation that is largely independent of SAM size.