{"title":"CMOS analog front-end for conversational video phone modem","authors":"C. Solomon, L. Ozcolak, G. Sellani, W. E. Brisco","doi":"10.1109/CICC.1989.56706","DOIUrl":null,"url":null,"abstract":"A description is given of an analog front-end chip relating to a video phone for transmission of audio signals and freeze-frame video images over voice-grade telephone lines. The device is implemented in a 3-μm CMOS process, utilizes switched-capacitor circuit technology and contains major functional blocks, such as a synchronous demodulator, transmit/receive filters, baseband and interpolating filters, an 8-bit digital-to-analog converter, a programmable gain amplifier, and clock and carrier recovery circuits. The chip occupies 27000 mil2 and dissipates 100 mW. System and circuit aspects of the design are discussed","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"104 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56706","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A description is given of an analog front-end chip relating to a video phone for transmission of audio signals and freeze-frame video images over voice-grade telephone lines. The device is implemented in a 3-μm CMOS process, utilizes switched-capacitor circuit technology and contains major functional blocks, such as a synchronous demodulator, transmit/receive filters, baseband and interpolating filters, an 8-bit digital-to-analog converter, a programmable gain amplifier, and clock and carrier recovery circuits. The chip occupies 27000 mil2 and dissipates 100 mW. System and circuit aspects of the design are discussed