0.6-μm 12 K-gate ECL gate array with RAM and ROM

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56763

T. Nishimura, H. Satoh, M. Tatsuki, A. Ohba, S. Hine, K. Uga, Y. Kuramitsu

引用次数: 0

Abstract

A 12 K-gate ECL (emitter-coupled logic) gate array with dedicated memory has been developed using 0.6-μm bipolar process technology. The memory is available for RAM or ROM storage. The gate array can also be used to implement a configurable RAM having internal cells

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带有RAM和ROM的12 k栅极ECL栅极阵列

采用0.6 μm双极工艺技术，开发了一种12 k栅极专用存储器ECL(发射器耦合逻辑)栅极阵列。内存可用于RAM或ROM存储。门阵列还可用于实现具有内部单元的可配置RAM

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1989 Proceedings of the IEEE Custom Integrated Circuits Conference

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