Fast Defect Reduction to Enable Customer Yield Ramp

Abstract

Minimizing defects on production wafers is critical for fab yield ramp and high volume manufacturing. Understanding the defect reduction process is essential for successfully implementing and validating corrective measures. A structured approach to defect root cause identification and correction is essential for achieving increasingly smaller defects with technology scaling from 28nm planar to 7 nm FINFET and with increasing stacks of 3DNAND memory. Such an approach leverages a defect knowledge base, broad equipment design and process expertise, and proven best-known methods—in addition to state-of-the-art metrology, inspection, and analysis technologies.