Implementation of a Flexible Encoder for Structured Low-Density Parity-Check Codes

Abstract

The hardware implementation of an encoder for randomly generated low-density parity-check (LDPC) codes requires large area. Using structured LDPC codes decreases the encoding complexity and also provides design flexibility. In this paper, an architecture for implementing an encoder is presented that adheres to the structured LDPC codes defined in the IEEE 802.16e standard. The design methodology is flexible in terms of both the code rate and code length. Results are provided for an implementation on a Stratix FPGA for codes with rates 1/2, 2/3, 3/4 and 5/6, and block lengths ranging from 576-2304. The number of logic elements, clock speed, and throughput of the encoder for the different code lengths are presented. The design achieves encoding rates in excess of 400 Mbps.