Simplified recursive structure for turbo decoder with Log-MAP algorithm

Abstract

For the efficient implementation of a turbo decoder with Log-MAP (logarithm-maximum a posteriori) algorithm, we propose in this paper a solution with three highlights: the general core for forward and backward recursions, the simple branch metric calculation and a simplified rescaling of the path metrics. An FPGA (field programmable gate array) implementation with the proposed solution reduces area consumption to half and shows favorable performance.