Reliability analysis and mitigation of near threshold caches

Abstract

Energy reduction has become an important issue in the design of battery-powered devices for Internet of Things (IoT) applications. In this regard, lowering the supply voltage close to transistor threshold voltage, commonly known as Near Threshold Computing (NTC), has been a widely used approach to reduce the energy consumption of various designs. However, the energy-saving potential of NTC is hindered by various factors such as variation-induced functional failures of caches. To address this issue and get utmost NTC benefits, we provide a comprehensive analysis of memory failure mechanisms and propose proper mitigation scheme for near threshold caches. In this work, aging and variation-induced memory failures are analyzed first by incorporating device and circuit level models. Afterwards, we employ Built-in Self- Test (BIST) to identify the lowest voltage limit at which each memory block can properly operate. Then, a mitigation scheme is developed by disabling unreliable portion of the cache and mapping their accesses to the reliable portion. Our evaluation using 16KByte cache shows the proposed mitigation scheme can effectively address permanent and transient memory failures and achieve more than 30% energy-saving of near threshold caches with less than 10% reduction in effective cache size and almost negligible increase in cache miss rate.