Concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) Pub Date : 2004-01-27 DOI:10.1109/ASPDAC.2004.1337685

R. Zhan, H. Feng, Qiong Wu, X. Guan, Guang Chen, Haolu Xie, Albert Z. H. Wang

引用次数: 3

Abstract

On-chip ESD (electrostatic discharging) protection is a challenging IC design problem New CAD tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification, which has been used to develop the first intelligent CAD tool of such kind. Design examples in 0.35μm BiCMOS are presented.

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基于功能的布图级ESD保护电路设计验证中ESD关键参数的概念及提取方法

片内ESD(静电放电)保护是一个具有挑战性的IC设计问题，新的CAD工具对于全芯片水平的ESD保护设计预测和验证至关重要。本文提出了一种基于功能的布图级ESD保护电路设计验证中ESD关键参数的新概念和提取方法，并用于开发同类智能CAD工具。给出了0.35μm BiCMOS的设计实例。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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