The T9 transputer: A practical example of the application of standard test techniques

Abstract

The authors outline a practical approach adopted to integrated current design-for-test methodologies into a VLSI chip containing several processing elements and embedded RAM. It is shown that optimizing design styles to suit the applications has resulted in the need for more than one test strategy. Global design rules concerning clocking and reset to allow scan and behavioral test are discussed. Using the T9000 virtual channel processor as an example, the integration of some of these techniques is explained.