{"title":"Dual-level LVDS technique for reducing the data transmission lines by half of LCD driver IC","authors":"Doo-Hwan Kim, Sung-Hyun Yang, Kyoung-Rok Cho","doi":"10.1109/ESSCIR.2004.1356682","DOIUrl":null,"url":null,"abstract":"A dual low-voltage differential signalling (DLVDS) circuit has been proposed, aimed at reducing the number of transmission lines for an LCD driver IC. In the proposed circuit, we apply a pair of primitive data to the DLVDS circuit as inputs. The inputs act as complementary signals. Then, a transmitter converts the two inputs to two kinds of fully differential level signals. Thus, only two transmission lines are required to transfer two primitive inputs while keeping the LVDS feature. The receiver recovers the original input data through a level decoding circuit. We designed the proposed circuit using 0.25 /spl mu/m CMOS technology. As a result, the circuit shows 1-Gbps/2-line data rate and 35 mW power consumption at 2.5 V supply voltage.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 30th European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIR.2004.1356682","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A dual low-voltage differential signalling (DLVDS) circuit has been proposed, aimed at reducing the number of transmission lines for an LCD driver IC. In the proposed circuit, we apply a pair of primitive data to the DLVDS circuit as inputs. The inputs act as complementary signals. Then, a transmitter converts the two inputs to two kinds of fully differential level signals. Thus, only two transmission lines are required to transfer two primitive inputs while keeping the LVDS feature. The receiver recovers the original input data through a level decoding circuit. We designed the proposed circuit using 0.25 /spl mu/m CMOS technology. As a result, the circuit shows 1-Gbps/2-line data rate and 35 mW power consumption at 2.5 V supply voltage.