Nonvolatile and Energy-Efficient FeFET-Based Multiplier for Energy-Harvesting Devices

Mengyuan Li, Xunzhao Yin, X. Hu, Cheng Zhuo
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引用次数: 11

Abstract

Energy-harvesting internet-of-things devices must deal with unstable power input. Nonvolatile processors (NVPs) can offer an effective solution. Compact and low-energy arithmetic circuits that can efficiently switch between computation and backup operations are highly desirable for NVP design. This paper introduces a nonvolatile ferroelectric field-effect transistors (FeFET)-based sequential multiplier with the ability to do continued calculation after a power outage, thus achieving zero backup overhead. We exploit the unique characteristics of FeFETs to construct key components of a sequential multiplier. The multiplier relies on a FeFET-based adder and a new FeFET-based latch to achieve compact area and low operating energy. Moreover, it uses the hysteretic characteristic of FeFETs to realize the storage capability, and hence is able to store, at no extra cost, the intermediate data of an operation in a nonvolatile manner. This property provides support for continued computation when power supplies may be intermittent. Simulation results show that, assuming the same technology node, the proposed FeFET-based multiplier saves up to 21% and 19% area than a conventional CMOS-based sequential multiplier of 4-bits and 8-bits, respectively. It also saves 32% and 73% less area compared with a CMOS-based array multiplier. Furthermore, the proposed design can offer up to 32%/23% energy saving per operation compared with a 4/8-bit CMOS-based sequential multiplier.
用于能量收集装置的非易失性和高能效的基于效应场效应的倍增器
能量收集物联网设备必须处理不稳定的电力输入。非易失性处理器(NVPs)可以提供有效的解决方案。紧凑和低能量的算术电路,能够有效地在计算和备份操作之间切换,是NVP设计非常需要的。本文介绍了一种基于非易失性铁电场效应晶体管(FeFET)的顺序乘法器,该乘法器能够在断电后继续计算,从而实现零备份开销。我们利用效应场效应管的独特特性来构造顺序乘法器的关键元件。该乘法器采用基于fet的加法器和基于fet的锁存器,实现了面积小、工作能量低的特点。此外,它利用效应场效应管的滞后特性来实现存储能力,因此能够以非易失性的方式存储操作的中间数据,而无需额外的成本。当电源可能是间歇性的时,此属性为继续计算提供支持。仿真结果表明,在相同的技术节点下,基于fet的乘法器比传统的4位和8位cmos顺序乘法器分别节省21%和19%的面积。与基于cmos的阵列乘法器相比,它还节省了32%和73%的面积。此外,与基于4/8位cmos的顺序乘法器相比,所提出的设计可以提供高达32%/23%的每次操作节能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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