Modification of SOVA-Based Algorithms for Efficient Hardware Implementation

Abstract

In this paper, a modified soft-output Viterbi algorithm (SOVA) is presented to enable efficent hardware implementation. The forward-only processing of the SOVA has an inherent lower latency than forward-backward algorithms such as BCJR and its offsprings, which are commonly used in iterative decoders. Thus, SOVA-based architectures require less parallelization and therefore hardware for the same data throughput. A simplification is proposed to the Battail rule (BR) SOVA to approximate the concurrent path reliability values with the corresponding metric differences. This simplified BR-SOVA (SB-SOVA) performs close to max-log-MAP. Furthermore, a novel hybrid decoding architecture is proposed that combines the simplicity of the original Hagenauer rule and the performance-preserving properties of the SB-SOVA to trade implementation complexity for decoding performance. The hybrid approach is evaluated with practical link-level simulations of the downlink data channel in LTE Rel-8.