A review analysis of parallel prefix adders for better performnce in VLSI applications

Abstract

The role of digital adder in Digital system design using Very Large Scale Integration (VLSI) technique is very important. The performance of low power VLSI based adder design has been affected by Propagation Delay (PD) problem. A survey of adder's availability for low power VLSI design with minimum PD is done with the help of Parallel prefix adders design. This paper clarified about the design and analysis of various Parallel Prefix Adders (PPA) also compared with the performance of these adders on the aspects of area, delay and power. From the investigation results it clears that the Kogge stone adder (KSA) is superior for the delay process, so the speed of the addition is automatically increased. But it takes more power consumption and area.