A mechanism for efficient context switching

P. Nuth, W. Dally
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引用次数: 30

Abstract

Context switches are slow in conventional processors because the entire processor state must be saved and restored, even if much of the restored state is not used before the next context switch. This unnecessary data movement is required because of the coarse granularity of binding between names and registers. The context cache is introduced, which binds variable names to individual registers. This allows context switches to be very inexpensive, since registers are only loaded and saved out as needed. Analysis shows that the context cache holds more live data than a multithreaded register file, and supports more tasks without spilling to memory. Circuit simulations show that the access time of a context cache is 7% greater than a conventional register file of the same size.<>
一种有效的上下文切换机制
在传统处理器中,上下文切换速度很慢,因为必须保存和恢复整个处理器状态,即使在下一次上下文切换之前没有使用恢复的大部分状态。这种不必要的数据移动是必需的,因为名称和寄存器之间的绑定粒度很粗。引入了上下文缓存,它将变量名绑定到各个寄存器。这使得上下文切换的成本非常低,因为寄存器只在需要时加载和保存。分析表明,上下文缓存比多线程寄存器文件保存更多的实时数据,并且支持更多的任务而不会溢出内存。电路模拟表明,上下文缓存的访问时间比相同大小的传统寄存器文件的访问时间要长7%。
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