A flexible FPGA-to-FPGA interconnect interface design and implementation

Abstract

In FPGA-based SoCs, interconnect bus such as PCIe and Ethernet has a separate physical layer and physical layer interface. The physical layer (PHY) consumes quite a few power consumption and area overhead. In this paper, we propose a flexible interconnect interface (Unified PHY Interface, UPI) based on FPGA and describe its design. More specifically, UPI can parse various packets automatically by adding an interface convertor between physical layer and upper layer. Thus, a flexible interconnect architecture can be realized by using UPI for each upper layer controller. We implemented UPI on two Xilinx Virtex-7 FPGAs with Synopsys PCIe and Serial RapidIO (SRIO) IP core to verify our design. Experimental results show that the resource utilization was reduced to 72. 8% of the original design.