Test power optimization techniques for CMOS circuits

Abstract

Three efficient test power optimization algorithms for CMOS circuits are studied in this paper. First, for delay-fault test pattern sets of ISCAS89 benchmarks, this algorithm can cut down 37.5% or more test power than the simulation-based annealing algorithm. Second, because approaches which use the Hamming distance between two input test patterns, to optimize the test power, cannot reduce as much power for ISCAS85 benchmarks as expected, a novel optimization approach that uses the power of an ideal circuit without delay, to optimize the test power is presented. Experimental results demonstrate that our approach can cut down 70.8% more test power than present approaches. Third, the influence of undetermined test bits on test power optimization is studied by changing the number of undetermined bits in test patterns. Experimental results demonstrate that with the increase of undetermined test bits, the un-optimized test power markedly decreases.