Fully integrated multilevel interconnect process for low cost sub-half-micron ASIC applications

Abstract

Back-end-of-the line (BEOL) interconnect process integration for sub-half-micron ASIC applications with both low-cost merit and appropriately high performance is presented. Borderless and stacked contact/via structures to reduce chip size and minimization of ILD thickness without performance degradation are achieved. Blind-CMP, selective tungsten CVD, and fluorine-TEOS ILD with low dielectric constant are selected with process simplification in mind.