A research on power complementary bipolar technology to prevent parasitic operation

Abstract

A 2 /spl mu/m design ruled, High-Densified, and Low-Power-Consuming Bipolar Integrated Circuit process has been developed. The breakdown voltage of the transistor is 15 V and it has a stable current driving capability at high current (about 1 A) due to the low saturation voltage between emitter and collector. NPN Tr. has been fabricated to prevent leakage current and has good Cut-Off frequency (fT=5 GHz) by using a polysilicon emitter. The characteristics of this process is a Double Epi Process to form a high concentrated N+BL in VPNP Tr. (that is the same as in NPN Tr.) which can protect the parasitic Tr. operation like Latch-Up Phenomenon (Ihold=26 mA, Pa-PNP Tr, hFE=4). And it also includes the IIL Device without an additional mask layer. This process is a low voltage, high current power complementary bipolar process that merges a variety of NPN, VPNP, LPNP, SPNP, IIL devices, and a diffusion resistor.