Design Considerations Towards Zero-Variability Resistive RAMs in HRS State

Abstract

Resistive RAM (RAM) intrinsic variability is widely recognized as a major hurdle for widespread adoption of the technology. Moreover, the deeper we go into the High Resistance State (HRS), the higher the variability. In this context, this paper proposes circuit level design strategies to mitigate HRS variability. During the RESET operation, the programming current is strictly controlled while the voltage across the RRAM cell is regulated. From a design standpoint, a write termination circuit is used to constantly sense the programming current and stop the RESET pulse when the preferred RESET current is reached. The write termination is combined with a voltage regulator which provides a strict control of the RESET voltage. The paper first reviews the RRAM variability phenomenon. Then, an optimized programming scheme is developed to control the HRS state to approach zero-variability. Compared to the classical fixed-pulse programming scheme, variability is reduced by 99%.