Design of an Energy Efficient Analog Two-Quadrant Multiplier Cell Operating in Weak Inversion

Abstract

Analog low precision arithmetic circuits offer a significantly higher energy efficiency than their digital counterparts, which makes them ideally suited for low precision neuromorphic processing circuits. An analog two-quadrant multiplier cell consisting of only two MOSFETs with multi-bit resolution is presented. It operates in weak inversion with the back-gate used as multiplicator input consuming less than 1 fJ per operation. A 22 nm FD-SOI CMOS technology is used for simulations.