An accelerated datapath width optimization scheme for area reduction of embedded systems

Abstract

Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and redesign a system to reach near an optimal value. The resulting effect is a long design time. In this paper, we introduce an effective scheme that accelerates design. A system-level pruning of design exploration space speeds up the optimization process. Through a single-pass simulation for a reference customization and a model for estimating and evaluating the system's performance, pruning of design space is achieved. Experimental results show that a substantial reduction in design time is possible.