Chip/package co-analysis and inductance extraction for fan-out wafer-level-packaging

Abstract

Advanced packaging technology integrates multiple dies closely with package routing for higher performance and lower power. However, electrical and magnetic field interaction between chip wires and package requires careful parasitic extraction. For the first time, we provide comprehensive CAD flows for extracting parasitic inductance elements in the package-to-die (P2D) interface layers. We propose new full-chip loop-based inductance extraction methodologies using halo ground and bundle creation. This extraction engine is integrated in our P2D flow to extract chip/package inductive coupling elements efficiently and accurately. Our extraction engine needs only 0.63s computing time with an average self and mutual inductance error of 2.8% and 5.3%.