Performance Optimization of Full Swing Adders For Future DSP & Machine Learning Applications Using 16 nm CMOS Process at High Temperatures

Abstract

This article reports the optimization of full-swing (rail-to-rail voltage swing) adders for the efficient realization of booth multipliers that have been considered as the vital blocks for majority of machine learning and DSP (digital-signal-processing) applications. The SPICE simulation results obtained by employing 16 nm CMOS process at 0.7 VDD indicates that 22-T-HFA with a power & delay of 1.23 µW & 15.84 Ps is best suitable for making high performance booth multipliers compared to 26-T-BFA (Power: 1.36 µW & Delay: 48.9 pS), 28-T-CMOSFA (Power: 0.65 µW & Delay: 42.28 pS), 26-T-HFA (Power: 0.94 µW & Delay: 33.53 pS) and 22-T-TFA (Power: 1.23 µW & Delay: 20.35 pS). Moreover, the thermal drift of speed and power of rail-to-rail voltage swing adders have been systematically investigated by sweeping the temperature from 303K to 383K. High speed rail-to-rail voltage swing adders based booth multipliers have emerged as a key component in the realization of MAC (multiply-accumulate) operations in future CNN computations based hardware platforms.