S. Koester, E. Kiewra, Yanning Sun, D. Neumayer, J. Ott, D. Sadana, D. Webb, J. Fompeyrine, J. Locquet, M. Sousa, R. Germann
{"title":"GaAs MOS Capacitors and Self-Aligned MOSFETs with HfO2 Gate Dielectrics","authors":"S. Koester, E. Kiewra, Yanning Sun, D. Neumayer, J. Ott, D. Sadana, D. Webb, J. Fompeyrine, J. Locquet, M. Sousa, R. Germann","doi":"10.1109/DRC.2006.305111","DOIUrl":null,"url":null,"abstract":"Introduction: The difficulty of increasing performance by scaling in sub-100 nm Si CMOS technology has renewed interest in the use of Ill-V channel materials for advanced VLSI CMOS [1]. GaAs is an attractive choice for this application, due to its relative maturity compared to other III-Vs, its high electron mobility (6x compared to Si), and its lattice matching with Ge. The main barrier towards implementing GaAs for VLSI applications is the difficulty of forming a high-quality gate insulator [2]-[6]. However, other problems also need to be overcome, including poor thermal stability, low implant activation, and the lack of a self-aligned contacting scheme. In this work, we seek to address the integration and gate dielectric issues. We have developed a self-aligned process for GaAs MOSFETs with HfO2 gate dielectrics, and demonstrate functional enhancementand depletion-mode devices. We have also characterized MOS capacitors with GaAs/u-Si/SiO2/HfO2 gate stacks, and found that these structures have much lower DA and improved thermal stability compared to HfO2 films directly on GaAs.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 64th Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2006.305111","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Introduction: The difficulty of increasing performance by scaling in sub-100 nm Si CMOS technology has renewed interest in the use of Ill-V channel materials for advanced VLSI CMOS [1]. GaAs is an attractive choice for this application, due to its relative maturity compared to other III-Vs, its high electron mobility (6x compared to Si), and its lattice matching with Ge. The main barrier towards implementing GaAs for VLSI applications is the difficulty of forming a high-quality gate insulator [2]-[6]. However, other problems also need to be overcome, including poor thermal stability, low implant activation, and the lack of a self-aligned contacting scheme. In this work, we seek to address the integration and gate dielectric issues. We have developed a self-aligned process for GaAs MOSFETs with HfO2 gate dielectrics, and demonstrate functional enhancementand depletion-mode devices. We have also characterized MOS capacitors with GaAs/u-Si/SiO2/HfO2 gate stacks, and found that these structures have much lower DA and improved thermal stability compared to HfO2 films directly on GaAs.