Non Inverting Differential Asymmetrical CMOS Comparator with Intrinsic Hysteresis and Adjustable Asymmetry

Abstract

A non inverting differential asymmetrical CMOS comparator with intrinsic hysteresis and adjustable asymmetry is presented in this paper. A widely tunable hysteresis window was obtained. The threshold voltage of the comparator is adjustable up to +150 mV of the input differential signal in 16 steps. The input differential signal is 400 mVpp with a frequency of 1 MHz. The bias current is 50 uA and the supply voltage is 3.3 V. The design was made in basic gpdk Cadence integrated circuits front to back 0.18 um CMOS technology. The response time was minimized and also the difference between the phases of the outputs was minimized. This comparator can be used, with good performance, in signal conditioning chains.