Hardware-Based Error Correction Systems for Hamming Codes: a Review of the Literature

Abstract

With the growing necessity for data transmission among technical devices, there is an increasing demand for error correction systems (ECS) that are highly effective and efficient. Consequently, researchers have been compelled to propose innovative ECS architectures and novel utilization strategies. These proposed models operate by emphasizing different key aspects. These aspects include minimizing the region and control usage, reducing time delays at the decoder for time-sensitive communication, and achieving enhanced correction capabilities for Hamming codes. This paper aims to explore the various hardware implementations of ECS for Hamming codes within the context of written communication. Furthermore, this research endeavor presents a benchmark in comparison to the most recent state-of-the-art approaches.