D. Khera, M. Cresswell, L. W. Linholm, G. Ramanathan, J. Buzzeo, A. Nagarajan
{"title":"Knowledge extraction techniques for expert system assisted wafer screening","authors":"D. Khera, M. Cresswell, L. W. Linholm, G. Ramanathan, J. Buzzeo, A. Nagarajan","doi":"10.1109/ISMSS.1990.66127","DOIUrl":null,"url":null,"abstract":"The authors describe a procedure for using induction-based classification techniques for identifying relationships between work-in-process (WIP) test structure data and future IC yield at wafer test on a wafer-by-wafer or lot-by-lot basis. The relationships are extracted from databases of previously processed WIP wafer test structure measurements and final wafer yield. They are presented in the form of rules relating WIP data to final yield. It is further shown that these rules, when incorporated into expert systems, can advise the human operator responsible for screening wafers which are likely to produce submarginal yield if processed to completion. These rules also identify the WIP test structure parameters and values which have historically provided the highest and lowest final wafer yields.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"276 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMSS.1990.66127","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
The authors describe a procedure for using induction-based classification techniques for identifying relationships between work-in-process (WIP) test structure data and future IC yield at wafer test on a wafer-by-wafer or lot-by-lot basis. The relationships are extracted from databases of previously processed WIP wafer test structure measurements and final wafer yield. They are presented in the form of rules relating WIP data to final yield. It is further shown that these rules, when incorporated into expert systems, can advise the human operator responsible for screening wafers which are likely to produce submarginal yield if processed to completion. These rules also identify the WIP test structure parameters and values which have historically provided the highest and lowest final wafer yields.<>