A Power Analysis Resistant DES Cryptographic Algorithm and Its Hardware Design

Abstract

To deal with the threat of power analysis to encryption device, a new power analysis resistant DES algorithm architecture is proposed, which is combined with "asymmetric" mask technique. And its digital hardware circuit is designed. Then its power analysis attack resistant ability is tested. Compared with non-protected DES, using nearly 5 times larger samples and attack time, the key of the proposed DES still cannot be gained through correlation power analysis. Experiment results show that the designed DES algorithm has a certain anti power analysis effect.