A Virtual Laboratory Package to Support Teaching of Logic Design and Computer Organization

Abstract

This paper presents a web based virtual laboratory package which provides a hierarchical module level logic design tool equipped with a logic simulator, a set of pre-designed experiments with a facility to add new experiments. The tool contains a repertoire of components and design functionalities and provides features for aiding learning through experiments. For complex experiments, such as CPU design, the tool provides an interface for specifying the controller abstractly as an algorithmic state machine. A set of techniques has been introduced in the tool for efficient simulation catering to the requirement of the lab. All the experiments can be conveniently conducted on a regular desktop or laptop computer and can be saved with user identification at any point and resumed later. This virtual lab has been successfully deployed to support several experiments of a post graduate level course at IIT Kharagpur.