FPGA implementation of a synchronous motor real-time emulator based on delta operator

Abstract

The aim of this paper is to examine the advantages of using delta-operator to design a digital system emulator for the real-time Hardware-In-the-Loop (HIL) simulation of an AC drive application. A synchronous motor has been taken as a case study. To suit high accuracy and increase the realism of the test, the use of high sampling frequency is crucial. A comparison with a classical shift-operator based emulator is made in terms of precision and stability of the system. The continuous-time state-space model of the motor has been taken as reference. The influence of the sampling period and the fixed-point arithmetic is quantified. To achieve a high computational time, an FPGA target has been chosen for implementing the real-time emulator (RTE). The design and the functional validation of the developed FPGA-based hardware architecture are presented. Finally, an HIL validation of an FPGA-based hysteresis current controller for synchronous motor drive is achieved. This validation is carried out using the developed synchronous motor RTE based on delta-operator.