Wafer edge Shallow Trench Isolation side wall defect reduction on advanced CMOS 0.13µm technology at 0.18µm equipment platform

Abstract

Nowadays sustaining semiconductor business needs competitiveness improvement which includes scaling down the technology node from CMOS 0.18μm to 0.13μm using similar equipment platforms. In this paper, the enabling new advances technology is through process improvement. The method is complicated and easily caused systematics wafer edge yield loss during initial technology development due to process margin and equipment capability. This paper presents an integrated engineering approach to improve sort yield especially at the wafer edge region. Shallow Trench Isolation (STI) deposition void that causes poly stringer defect is one of the major contributors of yield loss. The process improvement includes understanding caused of defect, process optimization approach that lead to re-design of the STI layout with Optical Proximity Correction (OPC) tagging. The improvement has successfully enable CMOS 0.13μm technology to process at CMOS 0.18μm equipment platform and implemented in production.